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RAMexio
- verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder
servo
- Verilog编写的辉盛9g舵机控制程序，clk：25MHz，输入角度（0~180），输出PWM，直接连到舵机引脚上即可使用-Verilog prepared Fraser 9g servo control procedures, clk: 25MHz, input angle (0 to 180), the output PWM, directly connected to the steering pin can be used
demo3
- 双通道PWM信号发生器，Verilog编写，带时能输出端-PWM TRANCER by verilog
DC_Motor_Main
- 基于FPGA的verilog语言，实现对直流电机的PWM控制，包括电路图、主程序、控制模块、测速模块等-Based on FPGAVeriloglanguage, realization of PWM control of DC motors, including circuit diagrams, master, control module, the speed module
pwm_8.7
- 基于verilog产生多路PWM波形。频率、脉宽可调。带有延时-Based verilog generate multiple PWM waveform.
fan_control
- Verilog 语言下的风扇转速监控以及风扇转速PWM控制-Verilog language,fan speed monitor and fan speed control by PWM
PWM_IP_test
- zynq-7000开发板 PWM IP核（VHDL和Verilog）-zynq-7000 PWM IP
bldc_motor_control_design_example
- 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA
music
- 利用PWM使蜂鸣器产生音乐的verilog源代码及《友谊地久天长》的电路设计-Generates a PWM buzzer music verilog source code and Auld Lang Syne circuit design
pwm_generate_module
- verilog编写的，用按键控制PWM波占空比。可以定义死区，用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.
Nexys4FFTDemo-master
- A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT output
duoluduoji
- FPGA多路舵机控制，转动任意角度，可例化，初学者应用((Using Verilog language production of 3 Road PWM signal to control 3 .))